![]() ![]() However, small delay faults on short paths may be undetectable even with advanced timing aware ATPG. In recent years small delay faults have gained increasing attention as possible indicators of marginal hardware. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Marginal hardware introduces severe reliability threats throughout the life cycle of a system. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. The paper at hand extends this approach to interconnect structures. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. Based on the analysis, the benefits and drawbacks of several accessible Tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic DesignĪutomation (EDA) tools. Pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay It also analyzes the relevant fault models, automatic test ![]() Improving test quality and creating new test methods, algorithms, and testĭesigns requires a comprehensive study of these delay defects. Small delay defects (SDDs) and hidden delay defects (HDDs)Īre of critical importance in industries today since they are the source of most test escapes and These defects may result in functional and delay-related circuit failures. As technology scales down, digital VLSI circuits are prone to many manufacturing defects. ![]()
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